135 search results - page 12 / 27 » Efficient tree topology for FPGA interconnect network |
CF
2007
ACM
15 years 1 months ago
2007
ACM
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
TCAD
2010
14 years 4 months ago
2010
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
ISPD
2006
ACM
15 years 3 months ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
LCN
2007
IEEE
15 years 4 months ago
2007
IEEE
- Multiple distribution trees and multiple description (MD) coding are highly robust since they provide redundancy both in network paths and data. However, MD coded streaming inclu...
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...