135 search results - page 19 / 27 » Efficient tree topology for FPGA interconnect network |
IJCAI
1997
14 years 11 months ago
1997
Marco Gori Dipartimento di Ingegneria deU'Informazione Universita di Siena Via Roma 56 53100 Siena, Italy Alessandro Sperduti Dipartimento di Informatica Universita di Pisa C...
DSD
2006
IEEE
15 years 1 months ago
2006
IEEE
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
—This paper describes a new low-power, area and pin efficient alternative to differential encoding for high performance chip-to-chip and backplane signaling. The technique, calle...
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ICDE
2005
IEEE
15 years 11 months ago
2005
IEEE
We address the problem of content-based dissemination of highly-distributed, high-volume data streams for stream-based monitoring applications and large-scale data delivery. Exist...
ICCAD
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton t...