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3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
15 years 11 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...
145
Voted
FCCM
2009
IEEE
189views VLSI» more  FCCM 2009»
15 years 11 months ago
Application Specific Customization and Scalability of Soft Multiprocessors
Although soft microprocessors are widely used in FPGAs, limited work has been performed regarding how to automatically and efficiently generate soft multiprocessors. In this paper...
Deepak Unnikrishnan, Jia Zhao, Russell Tessier
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
15 years 11 months ago
Concurrent core test for SOC using shared test set and scan chain disable
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
Gang Zeng, Hideo Ito
154
Voted
SEW
2006
IEEE
15 years 11 months ago
Pseudo-Exhaustive Testing for Software
Pseudo-exhaustive testing uses the empirical observation that, for broad classes of software, a fault is likely triggered by only a few variables interacting. The method takes adv...
D. Richard Kuhn, Vadim Okun
FPL
2005
Springer
89views Hardware» more  FPL 2005»
15 years 10 months ago
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck