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MTV
2006
IEEE
97views Hardware» more  MTV 2006»
15 years 11 months ago
Circuit Profiling Mechanisms for High-Level {ATPG}
—Our Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently generate test sequences, we nee...
Jorge Campos, Hussain Al-Asaad
VLSID
2005
IEEE
124views VLSI» more  VLSID 2005»
15 years 10 months ago
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
CP
2003
Springer
15 years 10 months ago
Identifying Inconsistent CSPs by Relaxation
How do we identify inconsistent CSPs quickly? This paper presents relaxation as one possible method; showing how we can generate relaxed CSPs which are easier to prove inconsistent...
Tomas Eric Nordlander, Ken N. Brown, Derek H. Slee...
EH
2000
IEEE
123views Hardware» more  EH 2000»
15 years 9 months ago
The Test Vector Problem and Limitations to Evolving Digital Circuits
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digit...
Kosuke Imamura, James A. Foster, Axel W. Krings
ASPDAC
1999
ACM
100views Hardware» more  ASPDAC 1999»
15 years 9 months ago
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition
: This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into sub...
Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Teru...