Sciweavers

7118 search results - page 1165 / 1424
» Electrical and Computer Engineering
Sort
View
KDD
2006
ACM
208views Data Mining» more  KDD 2006»
16 years 3 months ago
Frequent subgraph mining in outerplanar graphs
In recent years there has been an increased interest in frequent pattern discovery in large databases of graph structured objects. While the frequent connected subgraph mining pro...
Tamás Horváth, Jan Ramon, Stefan Wro...
122
Voted
VLSID
2008
IEEE
117views VLSI» more  VLSID 2008»
16 years 3 months ago
Single Event Upset: An Embedded Tutorial
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
Fan Wang, Vishwani D. Agrawal
VLSID
2007
IEEE
126views VLSI» more  VLSID 2007»
16 years 3 months ago
An ECO Technique for Removing Crosstalk Violations in Clock Networks
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama ...
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
16 years 3 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
16 years 3 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
« Prev « First page 1165 / 1424 Last » Next »