1379 search results - page 12 / 276 » Elements of low power design for integrated systems |
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
101
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VLSID
2010
IEEE
15 years 1 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
106
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ISVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
69
Voted
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
Low power technology is impacting our society by creating the newly emerging digital consumer market, which leads to the nomadic life-style. In this paper, historical review of th...