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ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
15 years 10 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
15 years 7 months ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...
SIGUCCS
2004
ACM
15 years 7 months ago
Research based methods for using powerpoint, animation, and video for instruction
This paper is a literature review on practical techniques and guidelines using PowerPoint, animation, and video effectively for instruction. The motivation to collect research bas...
Trevor Murphy
CODES
2002
IEEE
15 years 6 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
121
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ACSE
1997
ACM
15 years 6 months ago
Towards literate tools for novice programmers
Literate programming is a powerful technique that helps expert programmers integrate code and documentation in a manner that assists human comprehension. To date, tools for litera...
Andy Cockburn, Neville Churcher