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» Elements of low power design for integrated systems
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ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
15 years 2 months ago
ILP-based optimization of sequential circuits for low power
The power consumption of a sequential circuit can be reduced by decomposing it into subcircuits which can be turned off when inactive. Power can also be reduced by careful state e...
Feng Gao, John P. Hayes
ISCAS
2003
IEEE
156views Hardware» more  ISCAS 2003»
15 years 2 months ago
GNOMES: a testbed for low power heterogeneous wireless sensor networks
Continuing trends in sensor, semiconductor and communication systems technology (smaller, faster, cheaper) make feasible very dense networks of fixed and mobile wireless devices ...
Erik Welsh, Walt Fish, J. Patrick Frantz
84
Voted
LCPC
2004
Springer
15 years 2 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...
86
Voted
DFT
2005
IEEE
72views VLSI» more  DFT 2005»
15 years 3 months ago
Soft Error Modeling and Protection for Sequential Elements
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...
Hossein Asadi, Mehdi Baradaran Tahoori
67
Voted
VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
15 years 10 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...