Sciweavers

1379 search results - page 30 / 276
» Elements of low power design for integrated systems
Sort
View
ISVLSI
2007
IEEE
185views VLSI» more  ISVLSI 2007»
15 years 8 months ago
A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator
This paper presents a two-stage CMOS differential voltage-controlled ring oscillator (VCO). The VCO is intended to operate as a frequency synthesizer in a PLL to generate local os...
Luciano Severino de Paula, Eric E. Fabris, Sergio ...
DAC
2009
ACM
16 years 2 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
94
Voted
ISCAS
2005
IEEE
157views Hardware» more  ISCAS 2005»
15 years 7 months ago
High-efficiency power amplifier for wireless sensor networks
Abstract— We designed a high-efficiency class-E switchedmode power amplifier for a wireless networked micro-sensors system. In this system, where each sensor operates using a mic...
Devrim Yilmaz Aksin, Stefano Gregori, Franco Malob...
DAC
2007
ACM
16 years 2 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
ISPD
2009
ACM
79views Hardware» more  ISPD 2009»
15 years 8 months ago
A routing approach to reduce glitches in low power FPGAs
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
Quang Dinh, Deming Chen, Martin D. F. Wong