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» Elements of low power design for integrated systems
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MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 7 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
HOTOS
2009
IEEE
15 years 5 months ago
Mobility Changes Everything in Low-Power Wireless Sensornets
The system and network architecture for static sensornets is largely solved today with many stable commercial solutions now available and standardization efforts underway at the I...
Prabal Dutta, David E. Culler
126
Voted
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
15 years 7 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
HPCC
2007
Springer
15 years 8 months ago
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efï¬...
Yong Li, Zhiying Wang, Jian Ruan, Kui Dai
115
Voted
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
15 years 8 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng