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» Elements of low power design for integrated systems
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TC
2008
15 years 1 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
FTEDA
2008
75views more  FTEDA 2008»
15 years 2 months ago
Thermally Aware Design
With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today's heat sinks to limit the on-chip temperature. As a result, t...
Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
CODES
2000
IEEE
15 years 6 months ago
Parameterized system design
Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To b...
Tony Givargis, Frank Vahid
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
15 years 7 months ago
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus
The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account sin...
Marco Caldari, Massimo Conti, Massimo Coppola, Pao...
BMCBI
2006
182views more  BMCBI 2006»
15 years 2 months ago
A database and tool, IM Browser, for exploring and integrating emerging gene and protein interaction data for Drosophila
Background: Biological processes are mediated by networks of interacting genes and proteins. Efforts to map and understand these networks are resulting in the proliferation of int...
Svetlana Pacifico, Guozhen Liu, Stephen Guest, Jod...