10 search results - page 2 / 2 » Eliminating Conditional Branches for Enhancing Instruction L... |
MICRO
1994
IEEE
13 years 10 months ago
1994
IEEE
Branch instructions are recognized as a major impediment to exploiting instruction level parallelism. Even with sophisticated branch prediction techniques, many frequently execute...
MICRO
2000
IEEE
13 years 10 months ago
2000
IEEE
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
HPCA
1997
IEEE
13 years 10 months ago
1997
IEEE
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication. In compiler-synthesized dynamic branch prediction, the compiler g...
ICCD
2001
IEEE
14 years 3 months ago
2001
IEEE
General-purpose microprocessors augmented with SIMD execution units enhance multimedia applications by exploiting data level parallelism. However, supporting/overhead related inst...
CGO
2003
IEEE
13 years 11 months ago
2003
IEEE
Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the result update is co...