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ICCD
1993
IEEE
90views Hardware» more  ICCD 1993»
15 years 1 months ago
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Pee...
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CODES
2008
IEEE
15 years 4 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
DATE
2009
IEEE
229views Hardware» more  DATE 2009»
15 years 4 months ago
Health-care electronics The market, the challenges, the progress
— Exploding health care demands and costs of aging and stressed populations necessitate the use of more in-home monitoring and personalized health care. Electronics hold great pr...
Wolfgang Eberle, Ashwin S. Mecheri, Thi Kim Thoa N...
EWSA
2005
Springer
15 years 3 months ago
On the Systematic Conformance Check of Software Artefacts
Abstract. In this paper we present a systematic check of the conformance of the implemented and the intended software architecture. Nowadays industry is confronted with rapidly evo...
Hylke W. van Dijk, Bas Graaf, Rob Boerman
AES
2000
Springer
98views Cryptology» more  AES 2000»
15 years 2 months ago
How Well Are High-End DSPs Suited for the AES Algorithms? AES Algorithms on the TMS320C6x DSP
The National Institute of Standards and Technology (NIST) has announced that one of the design criteria for the Advanced Encryption Standard (AES) algorithm was the ability to eï¬...
Thomas J. Wollinger, Min Wang, Jorge Guajardo, Chr...