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DAC
2003
ACM
15 years 11 months ago
Using a formal specification and a model checker to monitor and direct simulation
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
Serdar Tasiran, Yuan Yu, Brannon Batson
CSUR
1999
114views more  CSUR 1999»
14 years 9 months ago
Directions for Research in Approximate System Analysis
useful for optimizing compilers [15], partial evaluators [11], abstract debuggers [1], models-checkers [2], formal verifiers [13], etc. The difficulty of the task comes from the fa...
Patrick Cousot
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
CN
2006
127views more  CN 2006»
14 years 10 months ago
A survey on communication networks for electric system automation
In today' s competitive electric utility marketplace, real-time information becomes the key factor for reliable delivery of power to the end-users, profitability of the electr...
Vehbi C. Gungor, Frank C. Lambert
DAC
2001
ACM
15 years 11 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...