The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC. The novel feature of the approach is the use an embedde...
Christos A. Papachristou, F. Martin, Mehrdad Noura...
Over the past decade, the trajectory to the petascale has been built on increased complexity and scale of the underlying parallel architectures. Meanwhile, software developers hav...
Abstract-- The PPV is a robust phase domain macromodel for oscillators. It has been proven to predict oscillators' responses correctly under small signal perturbations, and ca...
Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...