This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya,...
The idea of changing cache attributes to suit an application has been explored for single programs. As the popularity of reconfigurable softcore systems grows and these systems in...
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even ...
Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J....
Abstract. This paper addresses a new framework for designing and implementing skeleton libraries, in which each skeleton should not only be efficiently implemented as is usually d...
Portableembeddeddevicesmustpresentlyrunmultimediaandwireless network applications with enormous computational performance requirements at a low energy consumption. In these applica...
David Atienza, Stylianos Mamagkakis, Francky Catth...