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ICCD
2008
IEEE
167views Hardware» more  ICCD 2008»
15 years 9 months ago
Exploiting spare resources of in-order SMT processors executing hard real-time threads
— We developed an SMT processor that allows a static WCET analysis of several hard real-time threads and uses the remaining resources for soft or non real-time threads. The analy...
Jörg Mische, Sascha Uhrig, Florian Kluge, The...
123
Voted
RTAS
2008
IEEE
15 years 9 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
124
Voted
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
15 years 8 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
112
Voted
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
15 years 8 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
ISSS
1998
IEEE
124views Hardware» more  ISSS 1998»
15 years 6 months ago
Data-Path Synthesis of VLIW Video Signal Processors
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
Zhao Wu, Wayne Wolf