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129
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FPGA
2008
ACM
129views FPGA» more  FPGA 2008»
15 years 4 months ago
Efficient ASIP design for configurable processors with fine-grained resource sharing
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...
Quang Dinh, Deming Chen, Martin D. F. Wong
147
Voted
DAC
2007
ACM
16 years 3 months ago
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
Jia Yu, Jingnan Yao, Jun Yang 0002, Laxmi N. Bhuya...
VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
16 years 3 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
126
Voted
RTAS
2008
IEEE
15 years 9 months ago
A Modular Worst-case Execution Time Analysis Tool for Java Processors
Recent technologies such as the Real-Time Specification for Java promise to bring Java’s advantages to real-time systems. While these technologies have made Java more predictab...
Trevor Harmon, Martin Schoeberl, Raimund Kirner, R...
93
Voted
SAMOS
2007
Springer
15 years 8 months ago
On the Problem of Minimizing Workload Execution Time in SMT Processors
Abstract—Most research work on (Simultaneous Multithreading Processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a wor...
Francisco J. Cazorla, Enrique Fernández, Pe...