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JTRES
2010
ACM
15 years 5 months ago
Cyclic executive for safety-critical Java on chip-multiprocessors
Chip-multiprocessors offer increased processing power at a low cost. However, in order to use them for real-time systems, tasks have to be scheduled efficiently and predictably. I...
Anders P. Ravn, Martin Schoeberl
RTAS
2010
IEEE
15 years 3 months ago
A Bandwidth Reservation Strategy for Multiprocessor Real-Time Scheduling
—The problem of scheduling a set of tasks on a multiprocessor architecture is addressed. Tasks are assumed to be sporadic with arbitrary deadlines and may migrate between process...
Ernesto Massa, George Lima
CASES
2009
ACM
15 years 11 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
IFL
2005
Springer
207views Formal Methods» more  IFL 2005»
15 years 10 months ago
A Dependently Typed Framework for Static Analysis of Program Execution Costs
Abstract. This paper considers the use of dependent types to capture information about dynamic resource usage in a static type system. Dependent types allow us to give (explicit) p...
Edwin Brady, Kevin Hammond
ICCAD
2000
IEEE
95views Hardware» more  ICCAD 2000»
15 years 9 months ago
Test of Future System-on-Chips
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
Yervant Zorian, Sujit Dey, Mike Rodgers