Sciweavers

1957 search results - page 271 / 392
» Embedded Processor Security
Sort
View
LCTRTS
2001
Springer
15 years 9 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
144
Voted
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 9 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
ICECCS
2000
IEEE
196views Hardware» more  ICECCS 2000»
15 years 9 months ago
Complexity: Concept, Causes and Control
Complexity arises from many sources – both within and outwith the system. Internal sources include modern hardware, e.g. super-scalar processors, and external sources include th...
John A. McDermid
EUROMICRO
1998
IEEE
15 years 9 months ago
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
ISSS
1998
IEEE
130views Hardware» more  ISSS 1998»
15 years 9 months ago
Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System
In this paper, we propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP proce...
Yin-Tsung Hwang, Yuan-Hung Wang