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ASPLOS
2004
ACM
15 years 10 months ago
Compiler orchestrated prefetching via speculation and predication
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
Rodric M. Rabbah, Hariharan Sandanagobalane, Mongk...
SAMOS
2004
Springer
15 years 10 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 10 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
168
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RTCSA
2003
IEEE
15 years 10 months ago
An Approximation Algorithm for Broadcast Scheduling in Heterogeneous Clusters
Network of workstation (NOW) is a cost-effective alternative to massively parallel supercomputers. As commercially available off-theshelf processors become cheaper and faster, it...
Pangfeng Liu, Da-Wei Wang, Yi-Heng Guo
CODES
2009
IEEE
15 years 9 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...