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ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 4 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
ESTIMEDIA
2008
Springer
15 years 1 months ago
Parallelization of belief propagation method on embedded multicore processors for stereo vision
Markov random field models provide a robust formulation of low-level vision problems. Among the problems, stereo vision remains the most investigated field. The belief propagation...
Chi-Hua Lai, Kun-Yuan Hsieh, Shang-Hon Lai, Jenq K...
WMPI
2004
ACM
15 years 5 months ago
Addressing mode driven low power data caches for embedded processors
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
Ramesh V. Peri, John Fernando, Ravi Kolagotla
LCTRTS
2007
Springer
15 years 6 months ago
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration o
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...
Richard Vincent Bennett, Alastair Colin Murray, Bj...
DAC
2007
ACM
16 years 25 days ago
A System For Coarse Grained Memory Protection In Tiny Embedded Processors
Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no...
Ram Kumar, Akhilesh Singhania, Andrew Castner, Edd...