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CODES
2005
IEEE
15 years 10 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 10 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
IEEEPACT
2005
IEEE
15 years 10 months ago
Memory Coloring: A Compiler Approach for Scratchpad Memory Management
Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in perfor...
Lian Li 0002, Lin Gao 0002, Jingling Xue
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
15 years 10 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
RTAS
2005
IEEE
15 years 10 months ago
Hybrid Supervisory Utilization Control of Real-Time Systems
Feedback control real-time scheduling (FCS) aims at satisfying performance specifications of real-time systems based on adaptive resource management. Existing FCS algorithms often...
Xenofon D. Koutsoukos, Radhika Tekumalla, Balachan...