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CODES
2005
IEEE
15 years 3 months ago
Enhanced code density of embedded CISC processors with echo technology
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even ...
Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J....
ICCD
2006
IEEE
124views Hardware» more  ICCD 2006»
15 years 6 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili
ICCD
2004
IEEE
114views Hardware» more  ICCD 2004»
15 years 6 months ago
Low Energy, Highly-Associative Cache Design for Embedded Processors
Many embedded processors use highly associative data caches implemented using a CAM-based tag search. When high-associativity is desirable, CAM designs can offer performance advan...
Alexander V. Veidenbaum, Dan Nicolaescu
HIPEAC
2009
Springer
15 years 4 months ago
Parallel H.264 Decoding on an Embedded Multicore Processor
In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inte...
Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurli...
ASAP
2000
IEEE
102views Hardware» more  ASAP 2000»
15 years 1 months ago
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...