Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
While the dynamic voltage scaling (DVS) techniques are efficient in reducing the dynamic energy consumption for the processor, varying voltage alone becomes less effective for t...
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...