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ECRTS
2005
IEEE
15 years 5 months ago
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Antonio Martí Campoy, Isabelle Puaut, Angel...
ISCAS
2005
IEEE
128views Hardware» more  ISCAS 2005»
15 years 5 months ago
Development of an audio player as system-on-a-chip using an open source platform
— Open source software are becoming more widely-used, notably in the server and desktop applications. For embedded systems development, usage of open source software can also red...
Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rai...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 5 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
RTAS
2005
IEEE
15 years 5 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
15 years 5 months ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir