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ISCAS
2006
IEEE
116views Hardware» more  ISCAS 2006»
15 years 3 months ago
Neural network stream processing core (NnSP) for embedded systems
Abstract— NnSP is a stream-based programmable and codelevel statically reconfigurable processor for realization of neural networks in embedded systems. NnSP is provided with a n...
Hadi Esmaeilzadeh, Pooya Saeedi, Babak Nadjar Araa...
ISSS
1996
IEEE
143views Hardware» more  ISSS 1996»
15 years 2 months ago
DSP Processor/Compiler Co-Design: A Quantitative Approach
In the paper the problem of processor/compiler codesign for digital signal processing and embedded SYstems is discussed. The main principle we follow is the top-down approach char...
Vojin Zivojnovic, Stefan Pees, C. Schälger, M...
EUROPAR
2004
Springer
15 years 3 months ago
Feasibility of QoS for SMT
Since embedded systems require ever more compute power, SMT processors are viable candidates for future high performance embedded processors. However, SMTs exhibit unpredictable pe...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
ASAP
1997
IEEE
92views Hardware» more  ASAP 1997»
15 years 1 months ago
Optimized software synthesis for synchronous dataflow
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable ...
Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 3 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...