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SAC
2010
ACM
15 years 22 days ago
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
Pavel Ghosh, Arunabha Sen
112
Voted
BMCBI
2005
103views more  BMCBI 2005»
15 years 13 days ago
SeqDoC: rapid SNP and mutation detection by direct comparison of DNA sequence chromatograms
Background: This paper describes SeqDoC, a simple, web-based tool to carry out direct comparison of ABI sequence chromatograms. This allows the rapid identification of single nucl...
Mark L. Crowe
CODES
2009
IEEE
15 years 7 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
SCAM
2006
IEEE
15 years 6 months ago
Evaluating C++ Design Pattern Miner Tools
Many articles and tools have been proposed over the years for mining design patterns from source code. These tools differ in several aspects, thus their fair comparison is hard. B...
Lajos Jeno Fülöp, Tamas Gyovai, Rudolf F...
96
Voted
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
15 years 5 months ago
Automated Bus Generation for Multiprocessor SoC Design
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
Kyeong Keol Ryu, Vincent John Mooney