We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
In this paper, we systematically define three transaction level TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP...
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
In this paper, we describe our work in progress on the reasoning module of ec(h)o, an augmented audio-reality interface for museum visitors utilizing spatialized soundscapes and a...
We present Saltate!, a wireless prototype system to support beginners of ballroom dancing. Saltate! acquires data from force sensors mounted under the dancers' feet, detects ...