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RTAS
2008
IEEE
15 years 8 months ago
Schedulability Analysis of MSC-based System Models
Message Sequence Charts (MSCs) are widely used for describing interaction scenarios between the components of a distributed system. Consequently, worst-case response time estimati...
Lei Ju, Abhik Roychoudhury, Samarjit Chakraborty
CODES
2007
IEEE
15 years 8 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
DATE
2007
IEEE
157views Hardware» more  DATE 2007»
15 years 8 months ago
Energy evaluation of software implementations of block ciphers under memory constraints
Software implementations of modern block ciphers often require large lookup tables along with code size increasing optimizations like loop unrolling to reach peak performance on g...
Johann Großschädl, Stefan Tillich, Chri...
ECRTS
2007
IEEE
15 years 8 months ago
Cache-Aware Timing Analysis of Streaming Applications
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
Samarjit Chakraborty, Tulika Mitra, Abhik Roychoud...
LCTRTS
2007
Springer
15 years 8 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier