823 search results - page 39 / 165 » Embedded Robustness Ips |
111
Voted
ACSAC
2010
IEEE
14 years 3 months ago
2010
IEEE
We present a quantitative lower bound on the number of vulnerable embedded device on a global scale. Over the past year, we have systematically scanned large portions of the inter...
101
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MTDT
2003
IEEE
15 years 4 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
114
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DT
2006
14 years 11 months ago
2006
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
121
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GECCO
2008
Springer
15 years 20 days ago
2008
Springer
In this paper, a multiobjective (MO) learning approach to image feature extraction is described, where Pareto-optimal interest point (IP) detectors are synthesized using genetic p...
112
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VLSID
2004
IEEE
15 years 12 months ago
2004
IEEE
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...