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LCTRTS
2001
Springer
15 years 7 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
EUROMICRO
2000
IEEE
15 years 7 months ago
Task Assignment and Scheduling under Memory Constraints
Many DSP and image processing embedded systems have hard memory constraints which makes it difficult to find a good task assignment and scheduling which fulfill these constrain...
Radoslaw Szymanek, Krzysztof Kuchcinski
ICPPW
2000
IEEE
15 years 7 months ago
Flits: Pervasive Computing for Processor and Memory Constrained Systems
Many pervasive computing software technologies are targeted for 32-bit desktop platforms. However, there are innumerable 8, 16, and 32-bit microcontroller and microprocessor-based...
William Majurski, Alden Dima, Mary Laamanen
115
Voted
AES
2000
Springer
98views Cryptology» more  AES 2000»
15 years 7 months ago
How Well Are High-End DSPs Suited for the AES Algorithms? AES Algorithms on the TMS320C6x DSP
The National Institute of Standards and Technology (NIST) has announced that one of the design criteria for the Advanced Encryption Standard (AES) algorithm was the ability to e...
Thomas J. Wollinger, Min Wang, Jorge Guajardo, Chr...
134
Voted
EUROMICRO
1999
IEEE
15 years 6 months ago
Design Space Exploration in System Level Synthesis under Memory Constraints
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constra...
Radoslaw Szymanek, Krzysztof Kuchcinski