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» Embedded System Design for Network Time Synchronization
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DAC
2006
ACM
16 years 4 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
122
Voted
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 3 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
15 years 9 months ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...
WORDS
2005
IEEE
15 years 9 months ago
Delay Analysis for Statistical Real-Time Channels in Mobile Ad-Hoc Networks
Wireless devices that communicate using the IEEE 802.11 protocol can be used to create mobile ad-hoc networks (MANETs). Many interesting applications using MANETs are realizable i...
Min-Gu Lee, Sunggu Lee
116
Voted
PODC
2009
ACM
16 years 3 months ago
Tight bounds for clock synchronization
d Abstract] Christoph Lenzen Computer Engineering and Networks Laboratory (TIK) ETH Zurich, 8092 Zurich, Switzerland lenzen@tik.ee.ethz.ch Thomas Locher Computer Engineering and N...
Christoph Lenzen, Thomas Locher, Roger Wattenhofer