3134 search results - page 111 / 627 » Embedded System Design for Network Time Synchronization |
179
click to vote
ECRTS
2009
IEEE
15 years 1 months ago
2009
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
116
click to vote
ISCAS
2006
IEEE
15 years 9 months ago
2006
IEEE
— Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the tim...
150
click to vote
CODES
2006
IEEE
15 years 9 months ago
2006
IEEE
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...
134
click to vote
SOFSEM
2007
Springer
15 years 9 months ago
2007
Springer
Digital technology is increasingly deployed in safety-critical situations. This calls for systematic design and verification methodologies that can cope with three major sources o...
137
Voted
CBSE
2008
Springer
15 years 5 months ago
2008
Springer
Abstract. In this paper we focus on design of a class of distributed embedded systems that primarily perform real-time controlling tasks. We propose a two-layer component model for...