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132
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ECRTS
2002
IEEE
15 years 9 months ago
2002
IEEE
For priority based buses such as CAN, worst case response time analysis is able to determine whether messages always meet their deadlines. This can include system models with boun...
130
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IMC
2009
ACM
15 years 11 months ago
2009
ACM
Triangle inequality violations (TIVs) are important for latency sensitive distributed applications. On one hand, they can expose opportunities to improve network routing by findi...
132
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DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
140
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IESS
2007
Springer
15 years 10 months ago
2007
Springer
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
150
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ISCA
2005
IEEE
15 years 10 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...