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USS
2004
15 years 6 months ago
Tor: The Second-Generation Onion Router
We present Tor, a circuit-based low-latency anonymous communication service. This second-generation Onion Routing system addresses limitations in the original design by adding per...
Roger Dingledine, Nick Mathewson, Paul F. Syverson
LCN
2003
IEEE
15 years 10 months ago
Evaluating System Performance in Gigabit Networks
- With the current wide deployment of Gigabit Ethernet technology in the backbone and workgroup switches, the network performance bottleneck has shifted for the first time in nearl...
Khaled Salah, K. El-Badawi
CASES
2001
ACM
15 years 8 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
15 years 11 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
RTAS
2008
IEEE
15 years 11 months ago
Schedulability Analysis of MSC-based System Models
Message Sequence Charts (MSCs) are widely used for describing interaction scenarios between the components of a distributed system. Consequently, worst-case response time estimati...
Lei Ju, Abhik Roychoudhury, Samarjit Chakraborty