Sciweavers

1042 search results - page 135 / 209
» Embedded Systems Design: Optimization Challenges
Sort
View
CASES
2001
ACM
15 years 7 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 9 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
DAC
2004
ACM
16 years 4 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
CODES
2006
IEEE
15 years 9 months ago
Resource virtualization in real-time CORBA middleware
Middleware for parallel and distributed systems is designed to virtualize computation and communication resources so that a more and consistent view of those resources is presente...
Christopher D. Gill
SIGMOD
2007
ACM
144views Database» more  SIGMOD 2007»
16 years 3 months ago
Efficient xml data dissemination with piggybacking
Content-based dissemination of XML data using the publishsubscribe paradigm is an effective means to deliver relevant data to interested data consumers. To meet the performance ch...
Chee Yong Chan, Yuan Ni