This paper presents the main results of a three-year long field and design study of proactive information technology in the home. This technology uses sensors to track human activ...
Ilpo Koskinen, Kristo Kuusela, Katja Battarbee, An...
Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym proble...
This paper considers the elements and challenges of heterogeneous data management and interdisciplinary collaboration, drawing from the literatures on participatory design, comput...
Karen S. Baker, Steven J. Jackson, Jerome R. Wanet...
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
As device geometries continue to shrink, single event upsets are becoming of concern to a wider spectrum of system designers. These “soft errors” can be a nuisance or catastro...