Sciweavers

5186 search results - page 806 / 1038
» Embedded Systems
Sort
View
DAC
2003
ACM
16 years 7 months ago
An IDF-based trace transformation method for communication refinement
In the Artemis project [13], design space exploration of embedded systems is provided by modeling application behavior and architectural performance constraints separately. Mappin...
Andy D. Pimentel, Cagkan Erbas
DAC
2004
ACM
16 years 7 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
16 years 6 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
VLDB
2005
ACM
177views Database» more  VLDB 2005»
16 years 6 months ago
Indexing mobile objects using dual transformations
With the recent advances in wireless networks, embedded systems and GPS technology, databases that manage the location of moving objects have received increased interest. In this ...
George Kollios, Dimitris Papadopoulos, Dimitrios G...
CISIS
2009
IEEE
16 years 23 days ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...