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CN
2002
77views more  CN 2002»
15 years 2 months ago
Architecture of a Web server accelerator
We describe the design, implementation and performance of a high-performance Web server accelerator which runs on an embedded operating system and improves Web server performance ...
Junehwa Song, Arun Iyengar, Eric Levy-Abegnoli, Da...
CODES
2009
IEEE
15 years 9 months ago
FRA: a flash-aware redundancy array of flash storage devices
Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage med...
Yangsup Lee, Sanghyuk Jung, Yong Ho Song
BMCBI
2007
157views more  BMCBI 2007»
15 years 2 months ago
Constructing gene co-expression networks and predicting functions of unknown genes by random matrix theory
Background: Large-scale sequencing of entire genomes has ushered in a new age in biology. One of the next grand challenges is to dissect the cellular networks consisting of many i...
Feng Luo, Yunfeng Yang, Jianxin Zhong, Haichun Gao...
NDSS
2006
IEEE
15 years 8 months ago
Protocol-Independent Adaptive Replay of Application Dialog
For many applications—including recognizing malware variants, determining the range of system versions vulnerable to a given attack, testing defense mechanisms, and filtering m...
Weidong Cui, Vern Paxson, Nicholas Weaver, Randy H...
SIGSOFT
2006
ACM
15 years 8 months ago
Bit level types for high level reasoning
Bitwise operations are commonly used in low-level systems code to access multiple data fields that have been packed into a single word. Program analysis tools that reason about s...
Ranjit Jhala, Rupak Majumdar