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» Embedded Timing Analysis: A SoC Infrastructure
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DT
2002
55views more  DT 2002»
13 years 10 months ago
Embedded Timing Analysis: A SoC Infrastructure
Sassan Tabatabaei, André Ivanov
IESS
2007
Springer
92views Hardware» more  IESS 2007»
14 years 4 months ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer
RSP
2005
IEEE
131views Control Systems» more  RSP 2005»
14 years 3 months ago
Models for Embedded Application Mapping onto NoCs: Timing Analysis
Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of N...
César A. M. Marcon, Márcio Eduardo K...
DSD
2009
IEEE
105views Hardware» more  DSD 2009»
14 years 4 months ago
Design of a Highly Dependable Beamforming Chip
—As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip 1 is designe...
Xiao Zhang, Hans G. Kerkhoff
EMSOFT
2009
Springer
14 years 4 months ago
Handling mixed-criticality in SoC-based real-time embedded systems
System-on-Chip (SoC) is a promising paradigm to implement safety-critical embedded systems, but it poses significant challenges from a design and verification point of view. In ...
Rodolfo Pellizzoni, Patrick O'Neil Meredith, Min-Y...