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SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
15 years 5 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
CODES
2005
IEEE
15 years 5 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
15 years 5 months ago
C Compiler Retargeting Based on Instruction Semantics Models
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compil...
Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, ...
INFOVIS
2005
IEEE
15 years 5 months ago
Visualizing Coordination In Situ
Exploratory visualization environments allow users to build and browse coordinated multiview visualizations interactively. As the number of views and amount of coordination increa...
Chris Weaver
IRI
2005
IEEE
15 years 5 months ago
Issues of hierarchical heterogeneous modeling in component reusability
Heterogeneous systems are systems that obey different functioning laws. For instance, during the design of embedded systems, it is generally necessary to study both the controller...
Aimé Mokhoo Mbobi, Frédéric B...