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88
Voted
DAC
2000
ACM
16 years 18 days ago
System chip test: how will it impact your design?
A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challeng...
Yervant Zorian, Erik Jan Marinissen
91
Voted
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
16 years 9 hour ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
63
Voted
DATE
2007
IEEE
91views Hardware» more  DATE 2007»
15 years 6 months ago
Remote testing and diagnosis of System-on-Chips using network management frameworks
This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both on-chip design-for-test (...
Oussama Laouamri, Chouki Aktouf
SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
15 years 5 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...
82
Voted
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
15 years 6 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...