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» Embedded core testing using genetic algorithms
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ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
15 years 6 months ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
87
Voted
JSS
2010
104views more  JSS 2010»
14 years 6 months ago
Using hybrid algorithm for Pareto efficient multi-objective test suite minimisation
Test suite minimisation techniques seek to reduce the effort required for regression testing by selecting a subset of test suites. In previous work, the problem has been considere...
Shin Yoo, Mark Harman
IWANN
1995
Springer
15 years 3 months ago
Test Pattern Generation for Analog Circuits Using Neural Networks and Evolutive Algorithms
This paper presents a comparative analysis of neural networks, simulated annealing, and genetic algorithms in the determination of input patterns for testing analog circuits. The ...
José Luis Bernier, Juan J. Merelo Guerv&oac...
ICANNGA
2011
Springer
254views Algorithms» more  ICANNGA 2011»
13 years 11 months ago
Simulated Evolution (SimE) Based Embedded System Synthesis Algorithm for Electric Circuit Units (ECUs)
ECU (Electric Circuit Unit) is a type of embedded system that is used in automobiles to perform different functions. The synthesis process of ECU requires that the hardware should...
Umair F. Siddiqi, Yoichi Shiraishi, Mona Abo El Da...
DATE
2008
IEEE
77views Hardware» more  DATE 2008»
15 years 6 months ago
Re-Examining the Use of Network-on-Chip as Test Access Mechanism
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
Feng Yuan, Lin Huang, Qiang Xu