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MTDT
2003
IEEE
164views Hardware» more  MTDT 2003»
15 years 2 months ago
Applying Defect-Based Test to Embedded Memories in a COT Model
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
Robert C. Aitken
68
Voted
FPL
2005
Springer
86views Hardware» more  FPL 2005»
15 years 3 months ago
On the Reliability Evaluation of SRAM-Based FPGA Designs
Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate ...
Olivier Héron, Talal Arnaout, Hans-Joachim ...
CSREAESA
2008
14 years 11 months ago
BIST-BASED Group Testing for Diagnosis of Embedded FPGA Cores
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
Alireza Sarvi, Carthik A. Sharma, Ronald F. DeMara
VLSID
2004
IEEE
212views VLSI» more  VLSID 2004»
15 years 10 months ago
On Design and Implementation of an Embedded Automatic Speech Recognition System
We present a new design of an Embedded Speech Recognition System. It combines the aspects of both hardware and software design to implement a speaker dependent, isolated word, sma...
Sujay Phadke, Rhishikesh Limaye, Siddharth Verma, ...
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
15 years 2 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...