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DATE
2007
IEEE
102views Hardware» more  DATE 2007»
15 years 4 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
CC
2011
Springer
270views System Software» more  CC 2011»
14 years 1 months ago
Subregion Analysis and Bounds Check Elimination for High Level Arrays
For decades, the design and implementation of arrays in programming languages has reflected a natural tension between productivity and performance. Recently introduced HPCS langua...
Mackale Joyner, Zoran Budimlic, Vivek Sarkar
ICSM
2003
IEEE
15 years 3 months ago
Software Architecture Recovery based on Pattern Matching
This paper is a summary of the author’s thesis that presents a model and an environment for recovering the high level design of legacy software systems based on user defined ar...
Kamran Sartipi
ARC
2010
Springer
183views Hardware» more  ARC 2010»
14 years 10 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
CCECE
2006
IEEE
15 years 3 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya