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» Embedded system synthesis under memory constraints
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ECRTS
2002
IEEE
15 years 2 months ago
Weakly Hard Real-time Constraints on Controller Area Network
For priority based buses such as CAN, worst case response time analysis is able to determine whether messages always meet their deadlines. This can include system models with boun...
Ian Broster, Guillem Bernat, Alan Burns
DAC
2006
ACM
15 years 10 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
AVSS
2006
IEEE
15 years 3 months ago
Real-Time Video Segmentation with VGA Resolution and Memory Bandwidth Reduction
This paper presents the implementation of a video segmentation unit used for embedded automated video surveillance systems. Various aspects of the underlying segmentation algorith...
Hongtu Jiang, Viktor Öwall, Håkan Ard&o...
SCOPES
2005
Springer
15 years 3 months ago
Software Synthesis from the Dataflow Interchange Format
Specification, validation, and synthesis are important aspects of embedded systems design. The use of dataflow-based design environments for these purposes is becoming increasingl...
Chia-Jui Hsu, Shuvra S. Bhattacharyya
RTCSA
2006
IEEE
15 years 3 months ago
Systematic Security and Timeliness Tradeoffs in Real-Time Embedded Systems
Real-time embedded systems are increasingly being networked. In distributed real-time embedded applications, e.g., electric grid management and command and control applications, i...
Kyoung-Don Kang, Sang Hyuk Son