Sciweavers

432 search results - page 46 / 87
» Embedded system synthesis under memory constraints
Sort
View
WORDS
2003
IEEE
15 years 3 months ago
ORB Middleware Evolution for Networked Embedded Systems
Standards-based COTS middleware has been shown to be effective in meeting a range of functional and QoS requirements for distributed real-time and embedded (DRE) systems. Each sta...
Christopher D. Gill, Venkita Subramonian, Jeff Par...
ICDCSW
2009
IEEE
15 years 4 months ago
Embedded Virtual Machines for Robust Wireless Control Systems
Embedded wireless networks have largely focused on openloop sensing and monitoring. To address actuation in closedloop wireless control systems there is a strong need to re-think ...
Rahul Mangharam, Miroslav Pajic
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
15 years 1 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
56
Voted
TROB
2002
64views more  TROB 2002»
14 years 9 months ago
Synthesis of deadlock prevention supervisors using Petri nets
Given an arbitrary Petri net (PN) structure, which may have uncontrollable and unobservable transitions, the deadlock prevention procedure presented here determines a set of linear...
Marian V. Iordache, John O. Moody, Panos J. Antsak...
ERSA
2004
134views Hardware» more  ERSA 2004»
14 years 11 months ago
A High Performance Application Representation for Reconfigurable Systems
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
Wenrui Gong, Gang Wang, Ryan Kastner