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» Embeddings into the Pancake Interconnection Network
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IPPS
1998
IEEE
13 years 10 months ago
Emulating Direct Products by Index-Shuffle Graphs
In the theoretical framework of graph embedding and network emulations, we show that the index-shuffle graph (a bounded-degreehypercube-like interconnection network, recently intr...
Bojana Obrenic
AINA
2007
IEEE
14 years 19 days ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 10 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
13 years 10 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
ITCC
2005
IEEE
13 years 12 months ago
A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs
The interconnection network plays an important role in the performance and energy consumption of a Networkon-Chip (NoC) system. In this paper, we propose a RDT(2,2,1)/α-based int...
Yang Yu, Mei Yang, Yulu Yang, Yingtao Jiang