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» Embeddings into the Pancake Interconnection Network
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DAC
1997
ACM
15 years 1 months ago
Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks
CAD tools and research in the area of reduced-order modeling of largelinearinterconnect networkshaveevolved from merely finding a Pad´e approximation for the given network trans...
Ibrahim M. Elfadel, David D. Ling
ETS
2006
IEEE
106views Hardware» more  ETS 2006»
15 years 3 months ago
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete ...
Vincent Kerzerho, Philippe Cauvet, Serge Bernard, ...
COLING
1990
14 years 10 months ago
Language Without A Central Pushdown Stack
We will attempt to show how human performance limitations on various types of syntactic embedding constructions in Germanic languages can be modelled in a relational network lingu...
Carson T. Schütze, Peter A. Reich
CASES
2005
ACM
14 years 11 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
ARC
2007
Springer
120views Hardware» more  ARC 2007»
15 years 1 months ago
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
Jae Young Hur, Stephan Wong, Stamatis Vassiliadis